Standard JEDEC compliant packages UTAC offers a broad array of JEDEC-compliant leadframe, laminate-based IC packages and application specific packaging solutions to meet your needs. Standard leadframe packages include TSOPs, QFPs and VQFNs with pin count range from 16 to 208. Laminate-based packages include FBGAs, stacked die MCPs, wCSPs, PBGAs and flip chip BGAs that can be designed to meet specific customer’s device performance and form factor requirements. For details on the pin count and body sizes of the package, please refer to our package datasheets from the left sidebar. Application specific and System-in-Package solutions To meet the increasing demand for higher degree of functional integration and smaller form factor for semiconductor IC products, UTAC has developed a range of application specific and System-in-package (SiP) solutions: These solutions leverages on UTAC’s design and process competence that integrate the latest packaging technology in substrate and packaging materials, thin wafer backgrind processing, die stacking and advanced wire bonding. Examples of these solutions include: Space saving: UTAC’s SiP-PBGA This is a 5 chips System in package that combines two Flash memories, two SRAM memories and one SOC chip in a single PBGA. This solution offers a footprint area saving of about 40% compared to packaging the component ICs individually using standard JEDEC packages(1). Better Thermal Performance: XP-FBGA UTAC’s XP-FBGA is a laminate-based BGA package that incorporates a built-in heat spreader for high power ICs. The XP-FBGA improves thermal dissipation by more than 14% under natural convection and more than 22% under forced convection compared to standard FBGA package(2). 3-D packaging: D2wCSP UTAC's D2wCSP is a 3-D packaging solution that packs two memory devices into a single package. This doubles the memory density without increasing package size. The D2wCSP can combine 2 identical memories, such as DRAM, or different devices such as DRAM + FLASH, DRAM + ASIC to enable customers to increase the functions and features of their product without increasing the package form factor. (1): Based on comparison of footprint area of JEDEC 35x35mm PBGA with the sum of four 12x20mm JEDEC TSOP48 and one 28x28 JEDEC PQFP208 Contact us, we will be happy to help you identify or tailor a packaging solution that meets your needs. Our assembly facility and equipment base Our assembly facility includes 65,000 square feet of Class 1K/10k clean rooms that is SAC-level 1 and QS9000 certified. We are equipped with the leading edge 300mm wafer processing equipment including wafer backgrinding and die attach. The table below lists the installed assembly equipment in our facility:
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