Leadtime Packages

Click any of the services to learn more.

3D SiP

Embedding of active die into substrate (in addition to passive components) to enable miniaturization through 3D assembly. UTAC partnered with leading supplier of embedded substrates to provide seamless turnkey solution from design to end of line. Using this solution can provide many benefits including:

  • Improved power, electrical and thermal efficiency
  • Two side cooling, shorter interconnects, power / ground planes.
  • Integration of RF and digital devices with isolation

Trend to 3D SiP w/ Embedded Chip

3D SiP Supply Chain Collaboration

Cu Clip

Copper Clip is a favorable replacement for traditional wire bond interconnection used for high performance MOSFETs. UTAC is in volume production for a variety of Cu Clip packages in support of leading IDM’s in the market.

UTAC Provides Fully Automated Assembly System with Thin Wafer Mount / Taiko Ring Cut & Removal. Target End Applications Include Industrial (High-End Computing Server / Data Centers) and Automotive. UTAC clip line configuration is suitable for multi chip / muli die configuration MOSFETs Dr MOS.

Cu Clip provides significant performance advantages allowing for higher current, higher frequency and better overall system efficiency:

  • Lower interconnect resistance and inductance
  • Lower spreading resistance
  • Improved current handling capability
  • Improved transient and steady state thermal performance

Turnkey Assembly & Test Solution in Thailand

Package QFN Cu Clip
Body Size Range 3.5 x 4.5 to 10 x 12 mm
Lead Count Range
Number of IC’s Range 1 to 3
Number of MOSFETs Range Up to 2
Number of Clips Range 1 to 3
Die Configuration Flexible Design (Stack or Side by Side)
Wire Type Range AuPdCu 1.0 to 1.5 mil, Au 1.0 to 1.5 mil


  • Current package types are running in high volume production for MEMS products in a assortment of body sizes, wire types, formfactor and multi-die designs.
  • UTAC R&D teams work closely with customers to ensure that the package design and the bill of materials selected to support the unique structure is optimized, robust and manufacturable.
  • MEMS devices running in high volume production include Oscillators, Magnetometer, Accelerometer, Gyroscope, Pressure, Thermometer and RF Tuners.
Enabling Cavity Package MEMS in support of Inertial, Pressure and Temperature Sensors Enabling Materials & Processes for MEMS Unique Structure Enabling Interposer Solutions for MEMS

Cavity Lid:

  • Material Selection and Properties
  • Plating Type
  • Pre-fabricated
  • Lid Attach Equipment can Support Glass, Plastic and
    Metal Lid Requirements
  • Multi-die Bonder can Support Precise Die Attach and
    Multi-Die Attach Requirements


  • Wafer Prep – Wafer Thinning
  • Die Attach – Thick BLT Control and Bleed
    using Silicone Materials
  • Wirebonding – on soft adhesives
  • Compression Mold for lower stress


  • Die Coating – Protect MEMS Device
    for Oscillator Applications
  • Film Over Wire
  • Wirebonding – on soft adhesives
  • Low Stress Materials – Die attach &
    Mold compound


  • Laminate Package –
    Coreless Technology
  • Routable QFN – Leadframe
  • Leadframe – Standard Gull
  • Ceramic – 2 Layers and

Wafer Level Processing

Wafer level services are available in various UTAC manufacturing locations. We support 200 / 300mm wafers up to 40nm ULK wafer nodes. UTAC can support a wide range of package sizes with bump pitch of 250um for a 150um bump diameter. Backside Surface Protection is an available option for our customers. We offer full turnkey solution from wafer probing, packaging to drop shipment arrangements. UTAC has in house second level reliability testing to support customer’s qualification requirements.


  • Die size from below 1x1mm
  • Backside Surface Protection option is available
  • Capable to process ULK devices up to 40nm wafer technology
Current Capability 2018 2019 – 2020
Wafer Size 8″ and 12″ wafer
Low K Capability 65nm, 40nm, 28nm 16nm
Die Size Support 0.76mm ~ 7mm 0.5mm ~ 18 > 18mm ~ 24
Die Thickness 200 um (12 in) / 185 um (8 in) / 150 um (12 in-NB) =/> 100 um =/> 50 um
Wafer Backgrind 150 um; Dry polishing; (Micro, Low, High bump) =/<100 um ultra thin; DBG
Saw Street Processing 62nm < 62 nm =/> 30 nm
WLP Protection – BSP 25um thickness
-IR/Non IR BSP Tape
– 2-in-1 Tape for Thin Wafer
Sidewall and Bump Protection
Laser Mark – Wafer ID Marking
– XY coordinate Marking
– Mark Through Tape
– Alpha Marking
– 2D Barcode Marking and Inspection
Wafer Singulation Mode and Inspection Metrology – Mech Saw
– Laser groove (Wide Beam/Pi Cut) + Mech saw
* Stealth Dicing
Remote/Plasma Dicing
Short Pulse LG+ Stealth Dicing
Tape & Reel (PnP & Testing Integration) – Automated 5-sided (5S) inspection
– Integrated Open/Short Test with 5S inspection
– Dual Bin Capable
– Integrated Unit Laser Mark (Thin Wafer)- Enhanced Post Seal Inspection (ePSI)
– Full Functional SDT with 5S
2D barcode inspection Integrated IR inspection
HVM Automated Full Functional Test with 5S (Singulated Die Testing)
Reliability Monitoring – Reel to Reel Automated
– 5-sided Inspection
– Reel to Reel Full Functional Test

* Capability demonstrated but w/o actual product – UTAC confidential

Colour Key: Qualified Capability Development