UTAC has a diverse capability spanning across nine factories in six countries in the Asia Pacific region. Packaging capability includes Leadless Packages, Wafer Level Packages, System in Package (SiP), Laminate Packages, Leaded Packages and Security Smart Card Module and Smart Card Inlay.
We integrate our service offerings to provide customers full-turnkey manufacturing solutions, including: bumping wafer probe, wafer processing, assembly, test, black-box encryption and direct shipment as designated by our customers.
Production capability at UTAC can support technology nodes up to 28nm and we can support 150mm, 200mm and 300mm wafer diameters in high volume production. All wire types and a wide range of wire diameter is running in high volume production today ranging from .6 mils to 2mils, Au, Pd Cu, Bare Cu, Au Alloy, Ag Alloy and AuPdCu.
Our solutions include 3D- SiP, Cu Clip, MEMS, Thin QFN, Multi-Row and/or Array, WLCSP, Side Wall Protection, Side Lead Plating inspectable joint (automotive grade accepted) and Security EAL 6 assembly.
Packaging Solutions
Click the following to learn more.
3D SiP
Embedding of active die into substrate (in addition to passive components) to enable miniaturization through 3D assembly. UTAC partnered with leading supplier of embedded substrates to provide seamless turnkey solution from design to end of line. Using this solution can provide many benefits including:
- Improved power, electrical and thermal efficiency
- Two side cooling, shorter interconnects, power / ground planes.
- Integration of RF and digital devices with isolation
Trend to 3D SiP w/ Embedded Chip
3D SiP Supply Chain Collaboration
Cu Clip
Copper Clip is a favorable replacement for traditional wire bond interconnection used for high performance MOSFETs. UTAC is in volume production for a variety of Cu Clip packages in support of leading IDM’s in the market.
UTAC Provides Fully Automated Assembly System with Thin Wafer Mount / Taiko Ring Cut & Removal.
Target end applications include Industrial (high-end computing server / data centers) and telecom infrastructure, laptop, graphics card and automotive.
UTAC clip line configuration is suitable for multi chip / muli die configuration MOSFETs Dr MOS and Smart power stage products.
Cu Clip provides significant performance advantages allowing for higher current, higher frequency and better overall system efficiency:
- Lower interconnect resistance and inductance
- Lower spreading resistance
- Improved current handling capability
- Improved transient and steady state thermal performance
Turnkey Assembly & Test Solution in Thailand
| Package | QFN Cu Clip |
|---|---|
| Body Size Range | 3.5 x 4.5 to 5 x 7mm |
| Lead Count Range | 8 to 41Ld |
| Number of IC’s Range | 1 to 3 |
| Clip Thickness | 5/6/8/10mil |
| Die Configuration | Flexible Design (Stack or Side by Side) |
| Wire Type Range | AuPdCu 1.0 to 1.5 mil, Au 1.0 to 1.5 mil |
MEMS
- Current package types are running in high volume production for MEMS products in a assortment of body sizes, wire types, formfactor and multi-die designs.
- UTAC R&D teams work closely with customers to ensure that the package design and the bill of materials selected to support the unique structure is optimized, robust and manufacturable.
- MEMS devices running in high volume production include Oscillators, Magnetometer, Accelerometer, Gyroscope, Pressure, Thermometer and RF Tuners.
| Enabling Cavity Package MEMS in support of Inertial, Pressure and Temperature Sensors | Enabling Materials & Processes for MEMS Unique Structure | Enabling Interposer Solutions for MEMS |
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Cavity Lid:
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Process:
Materials:
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Interposers:
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Enabling Cavity Package MEMS in support of Inertial, Pressure and Temperature Sensors
Cavity Lid:
- Material Selection and Properties
- Plating Type
- Pre-fabricated
- Lid Attach Equipment can Support Glass, Plastic and
Metal Lid Requirements - Multi-die Bonder can Support Precise Die Attach and
Multi-Die Attach Requirements
Enabling Materials & Processes for MEMS Unique Structure
Process:
- Wafer Prep – Wafer Thinning
- Die Attach – Thick BLT Control and Bleed
using Silicone Materials - Wirebonding – on soft adhesives
- Compression Mold for lower stress
Materials:
- Die Coating – Protect MEMS Device
for Oscillator Applications - Film Over Wire
- Wirebonding – on soft adhesives
- Low Stress Materials – Die attach &
Mold compound
Enabling Interposer Solutions for MEMS
Interposers:
- Laminate Package –
Coreless Technology - Routable QFN – Leadframe
based - Leadframe – Standard Gull
Wing - Ceramic – 2 Layers and
Above
Bumping
UTAC now offers and is able to deliver full turn-key solution in Singapore.
With our wide range of 300mm RDL/ Wafer Bumping services, we are now a single island solution provider.
UTAC Singapore Bumping Facility
- UTAC owned since 1 Jan 2021
- Completed purchase of all WLCSP bumping assets on Jan1, 2021
- All existing bumping / support employees and its management team joined UTAC, bringing with them 5-10 years of bumping experience
- Fully automated production with MES and ERP system, in operation since 2006
- Mass production yield >99.8%
- On Time Delivery rate >99%
- Product
- 300mm wafer bumping – Solder Bump, Copper Pillar Bump, Ti/Cu/Cu RDL (including option for thicker PBO of 9μm)
- WLCSP – Ball drop
- Capacity
- 12-14k wafers per month
- Able to expand to 35k wafers per month
- Clean room: 4,700 m2
- Class 100 1st Floor – Lithography and Dry processes
- Class 1K 2nd Floor – Plating and Wet Etch processes
| Process Type | Solder Bump (Lead Free) |
Cu Pillar Bump (Lead Free) |
WLCSP (Ball Drop) |
|---|---|---|---|
| Product |  |
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| Wafer Size | 300mm | ||
| Incoming Wafer Thickness | ≥ 500um | ||
| Bump Pitch (Array) | ≥ 130um | ≥ 35um | ≥ 200 um |
| Bump Structure | Ni/SnAg Cu/Ni/SnAg |
Cu/SnAg, Cu/Ni/SnAg |
SACxxx, LFxx |
| Bump material grade | Ultra Low Alpha grade available | Multi grades available | |
| UBM Structure | Sputtered: Ti/Cu | Sputtered: Ti/Cu | Sputtered: Ti/Cu Plated UBM: Cu |
| Min Technology Nodes (Qualified) |
28nm | 16nm | 16nm |
| Passivation Material | PI or PBO | ||
| Redistribution | L/S: 8/8um Cu RDL thickness: 10um |
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| Min. Bump Size / Height (Production) |
90um / 65um | 45um / 60um | 227um / 157um |
| These are qualified and/or in production. Beyond this requires feasibility assessment. Details of capabilities to be verified based on customer requirement. | |||
WLCSP Solution – 2P2M + BM
- 2 PBO + 1 Cu RDL + 1 Cu UBM + Ball Mount
- RDL : Ti /Cu /Cu
- UBM: Ti /Cu /Cu
- Solder Ball: SAC405 (Std) or LF35
- Ball Pitch 300~500 um
WLCSP
SAC Solder
CIS CSP
| Typical Layer Configuration |
Standard (um) |
Thicker PSV Option (um) |
|---|---|---|
| PBO1 | 7.5 | 9.0 |
| RDL Trace/ Pad Plated Cu | 4 | 5 |
| PBO2 | 7.5 | 9.0 |
| UBM Pad Plated Cu | 8-10 | |
Note: Thicker Cu RDL/UBM can be supported. Will review on case-by-case basis PI can be used as alternative to PBO
Wafer Level Processing
Wafer level services are available in various UTAC manufacturing locations. We support 200 / 300mm wafers up to 28nm ULK wafer nodes. UTAC can support a wide range of package sizes with bump pitch of 250um for a 150um bump diameter. Backside Surface Protection is an available option for our customers. We offer full turnkey solution from bumping/ball drop/RDL, wafer probing, packaging to drop shipment arrangements. UTAC has in house second level reliability testing to support customer’s qualification requirements.
Features:
- Die size from below 1x1mm
- Backside Surface Protection option is available
- Capable to process ULK devices up to 28nm wafer technology
| Technologies | Existing | |
|---|---|---|
| Wafer Size | 8in, 12in | |
| Wafer Tech Node | 65nm/40nm/28nm Low k | |
| Wafer Notch Design | V-Notch | |
| Die Size | 0.45 mm – 7 mm | |
| Die Thickness | 200um (12in-Bump) / 185um (8in-Bump) / 100um (12in-No Bump) / 150um (12in-bump ; In-line BG) | |
| Wafer Backgrind | Stand Alone, In-line with Dry polishing / Z2 – #8000 Mesh | |
| Saw Street Processing | 62um (LG&MS), 50um (MS) | |
| WLP Protection | – BSP 25um thickness – IR/Non IR BSP Tape – 2-in-1 Tape for Thin Wafer (<250um Si) |
Fan-out WLP |
| Wafer Laser Mark | – Wafer ID Marking – XY Coordinate Marking – Alpha Marking – Mark Through Tape |
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| AOI | – Sawn and Un-sawn wafer inspection | |
| Wafer Singulation Mode and Inspection Metrology | – Mech. Saw – Wafer level IR inspection (IR tape) – Laser groove (U-Groove &/Pi Cut) + Mech. Saw – LG beam size control (8.5+/- 0.5um) |
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| Tape & Reel (PnP & Testing Integration) and Inspection Metrology | – Automated 5-sided (5S) inspection – Integrated Open/Short Test with 5S inspection – Dual Bin capable – Integrated Unit Laser Mark (Thin wafer) – Enhanced Post Seal Inspection (ePSI) |
– Full Functional SDT with 5S – 2D Barcode Marking & Inspection |
| – MPW Processing | ||
| Reliability Monitoring | Reel to Reel Automated 5-sided Inspection Reel to Reel Full Functional Test |
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